The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a functional block diagram of a wireless system 100 according to the prior art is presented. The wireless system 100 includes an antenna 102, a transceiver 104, and a baseband processor 106. The transceiver 104 includes a duplexer 108, which communicates with the antenna 102. The duplexer 108 communicates with a first filter 110 and a power amplifier 112. The first filter 110 applies a frequency profile to data received from the duplexer 108, and communicates filtered data to a low noise amplifier (LNA) 114.
The LNA 114 communicates an amplified output to a second filter 116. The second filter 116 communicates a filtered output to first and second mixers 118-1 and 118-2. A local oscillator (LO) 120 generates a local oscillator signal, LOG, which is communicated to a frequency divider 122. The frequency divider 122 phase-shifts the incoming LOG signals into quadrature and in-phase signals, LOQ and LOI respectively. LOQ and LOI are separated by 90°, and may both have a frequency that is half of the incoming LOG frequency.
The frequency divider 122 communicates LOQ and LOI to the first and second mixers 118-1 and 118-2 and to third and fourth mixers 124-1 and 124-2. The first mixer 118-1 mixes the output of the second filter 116 with the LOQ signal, and outputs the result to a third filter 126. The second mixer 118-2 mixes the output of the second filter 116 with the LOI signal, and communicates the result to a fourth filter 128. The third and fourth filters 126 and 128 communicate outputs to first and second baseband amplifiers 130 and 132, respectively.
Outputs of the first and second baseband amplifiers 130 and 132 are communicated to the baseband processor 106. The baseband processor 106 communicates information to third and fourth baseband amplifiers 140 and 142. The third and fourth baseband amplifiers 140 and 142 communicate outputs to fifth and sixth filters 144 and 146, respectively. Outputs of the fifth and sixth filters 144 and 146 are labeled baseband in-phase, BBI, and baseband quadrature, BBQ, respectively.
The third mixer 124-1 mixes BBI with LOI, generating an in-phase radio frequency (RF) signal, RFI. The fourth mixer 124-2 mixes BBQ with LOQ, generating a quadrature signal, RFQ. The third and fourth mixers 124-1 and 124-2 communicate RFI and RFQ, respectively, to an RF amplifier 148. An amplified output of the RF amplifier 148 is communicated to a seventh filter 150, whose output is communicated to the power amplifier 112.
Referring now to FIG. 2, a functional schematic of a frequency divider 200, such as the frequency divider 122 of FIG. 1, according to the prior art is presented. A differential signal LOG, consisting of a positive signal LOG+ 202 and a negative signal LOG− 204, is received. The frequency divider 200 includes first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, and 228.
In various implementations, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, and 228 are metal oxide semiconductor field effect transistors (MOSFETs) that have gates, sources, and drains, although other transistor types may be used. The positive signal LOG+ 202 is communicated to the gates of the first and second transistors 206 and 208. The sources of the first and third transistors 206 and 210 communicate with a first terminal of a first resistance 230.
An opposite terminal of the first resistance 230 communicates with ground. The sources of the second and forth transistors 208 and 212 communicate with a first terminal of a second resistance 232. An opposite terminal of the second resistance 232 communicates with ground. The first and second resistances 230 and 232 have a resistance value approximately equal to a value R1. The sources of the fifth and sixth transistors 214 and 216 communicate with the drain of the first transistor 206. The sources of the seventh and eighth transistors 218 and 220 communicate with the drain of the third transistor 210.
The sources of the ninth and tenth transistors 222 and 224 communicate with the drain of the second transistor 208. The sources of the eleventh and twelfth transistors 226 and 228 communicate with the drain of the fourth transistor 212. The drains of the fifth and seventh transistors 214 and 218 and the gate of the eighth transistor 220 communicate with a first terminal of a third resistance 236. The drains of the sixth and eighth transistors 216 and 220 and the gate of the seventh transistor 218 communicate with a first terminal of a fourth resistance 238.
The drains of the ninth and eleventh transistors 222 and 226 and the gate of the tenth transistor 224 communicate with a first terminal of a fifth resistance 240. The drains of the tenth and twelfth transistors 224 and 228 and the gate of the ninth transistor 222 communicate with a first terminal of a sixth resistance 242. Opposite ends of the third, fourth, fifth, and sixth resistances 236, 238, 240, and 242 communicate with a supply potential, such as VDD.
The gate of the fifth transistor 214 communicates with the drain of the twelfth transistor 228 and is output from the frequency divider 200 as LOI+ 250. The gate of the sixth transistor 216 communicates with the drain of the eleventh transistor 226, and is output from the frequency divider 200 as LOI− 252. The gate of the eleventh transistor 226 communicates with the drain of the fifth transistor 214, and is output from the frequency divider 200 as LOQ− 254. The gate of the twelfth transistor 228 communicates with the drain of the sixth transistor 216, and is output from the frequency divider 200 as LOQ+ 256.
Even when the two signals LOG+ 202 and LOG− 204 of the differential signal are equal, mismatches between the first and third transistors 206 and 210 cause different amounts of current to flow through the first and third transistors 206 and 210. The mismatch between the first and third transistors 206 and 210 can be modeled as an offset voltage (VOS) source 260 interposed between the positive signal LOG+ 202 and the gate of the first transistor 206.
Mismatch between the second and fourth transistors 208 and 212 can be modeled as a second offset voltage source (not shown) between the positive signal LOG+ 202 and the gate of the second transistor 208. The second offset voltage source can be incorporated into the VOS source 260. These transistor mismatches translate into amplitude and phase mismatches in the output LOQ and LOI signals. Amplitude matching may be improved through the use of limiters following the frequency divider 200, but phase matching is much more difficult to restore once a mismatch has been introduced.
The resulting difference in currents between the first and third transistors 206 and 210 (input pair) can be described by the following equation:ΔIDC=I1Q−I2Q≈gm·VOS,where gm is the small signal transconductance of the input pair with an offset voltage VOS equal to zero, and I1Q and I2Q are the currents flowing through the first and third transistors 206 and 210, respectively. The current imbalance ΔIDC causes the zero crossing instant to shift in time and gives rise to IQ phase mismatch.
Referring now to FIG. 3, a functional schematic of a mixer 300 according to the prior art, such as the first, second, third, or fourth mixers 118-1, 118-2, 124-1, or 124-2 of FIG. 1, is presented. The mixer 300 includes first, second, third, fourth, fifth, and sixth transistors 302, 304, 306, 308, 310, and 312. In various implementations, the first, second, third, fourth, fifth, and sixth transistors 302, 304, 306, 308, 310, and 312 are metal oxide semiconductor field effect transistors (MOSFETs) that have gates, sources, and drains, although other transistor types may be used.
A positive signal of the local oscillator input, LOI+ 314, is received by the gates of the first and second transistors 302 and 304. The negative signal of the local oscillator input, LOI− 316, communicates with the gates of the third and fourth transistors 306 and 308. The positive signal of the in-phase baseband signal, BBI+ 318, communicates with the gate of the fifth transistor 310.
The negative signal of the in-phase baseband signal, BBI− 320, communicates with the gate of the sixth transistor 312. The sources of the fifth and sixth transistors 310 and 312 communicate with first terminals of first and second resistances 322 and 324, respectively. Opposite terminals of the first and second resistances 322 and 324 communicate with ground. The resistance values of the first and second resistances 322 and 324 are approximately equal to a value R1.
The drains of the first and fourth transistors 302 and 308 communicate with a first terminal of a third resistance 326, and also output a negative signal of the in-phase RF signal, RFI− 330. The drains of the second and third transistors 304 and 306 communicate with a first terminal of a fourth resistance 328, and also output a positive signal of the in-phase RF signal, RFI+ 332. Opposite terminals of the third and fourth resistances 326 and 328 communicate with a supply potential, such as VDD. Mismatch between the first and third transistors 302 and 306, and between the second and fourth transistors 304 and 308, cause amplitude and phase mismatch in the RFI signal.